As the technology for manufacturing integrated circuits advances, more logic functions are included in a single integrated circuit device, thereby increasing the number of gates on a single semiconductor device. The gates are interconnected to perform multiple and complex functions.
A manufacturing defect or a defect due to circuit aging may prevent the integrated circuit from performing all of the designed functions. To detect such errors, verification of the design of the integrated circuit device is conducted and various types of electrical tests are performed on the integrated circuit device. Those tests may, for example, be performed at manufacturing time (referred to in the art as a design for test (DFT)), or at system boot time. Now, for example in connection with safety-related applications, there is also a need to perform such tests at software runtime.
As the complexity of the integrated circuit device increases, so does the cost and complexity of verifying and electrically testing each of the elements in the integrated circuit. Modern integrated circuits usually incorporate a variety of design-for-test (DFT) structures to enhance their testability. Typically, the DFT structures are based on a scan design, where scan test data is provided to an input test pin, passed to a scan chain embedded into the integrated circuit, and executed by the logic of the circuit. The results of such execution are exported to an output test pin for evaluation. When in manufacturing test mode, the input test pin can be driven directly by automated test equipment (ATE). When in system operating mode, an on-chip self test function (for example, a built-in self test (BIST)) can provide the scan test data and evaluate the results of the execution.
In whatever circuit operating mode (i.e., manufacturing test mode, boot time test mode or system run time test mode), the testing can be a time consuming activity. Thus, there is interest in identifying ways to reduce the testing time, especially in the context of safety sensitive applications where system available needs to be optimized.
More particularly, in connection with the system run time test mode, it is important for the testing operation to interrupt run time operation of the system for as short a time duration as possible. Testing time includes the time taken to load the test pattern into the scan chain, the time taken to process the test pattern in the circuitry and the time take to read the test result out from the scan chain. In prior art schemes, it is known to stop the run time functional operation of the system, perform the test mode operation, and then resume the run time functional operation. This scheme induces a time penalty on system readiness since the run time functional operation has been interrupted to permit the test mode operation. There is a need in the art for a means to reduce the length of time that the run time functional operation is interrupted in support of test mode operation. There would be an advantage if the injection of a subsequent test pattern to the scan chain could be made during run time functional operation.